<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="6.x">Drupal-Biblio</source-app><ref-type>47</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Rimas Avizienis</style></author><author><style face="normal" font="default" size="100%">Freed, Adrian</style></author><author><style face="normal" font="default" size="100%">Suzuki, Takahiko</style></author><author><style face="normal" font="default" size="100%">Wessel, David</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">Scalable Connectivity Processor for Computer Music Performance Systems</style></title>
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<secondary-title><style face="normal" font="default" size="100%">International Computer Music Conference</style></secondary-title></titles><dates><year><style  face="normal" font="default" size="100%">2000</style></year></dates><urls><web-urls><url><style face="normal" font="default" size="100%">http://cnmat.berkeley.edu/publication/scalable_connectivity_processor_computer_music_performance_systems</style></url></web-urls></urls><publisher><style face="normal" font="default" size="100%">International Computer Music Association</style></publisher><pub-location><style face="normal" font="default" size="100%">Berlin, Germany</style></pub-location><pages><style face="normal" font="default" size="100%">523-526</style></pages><language><style face="normal" font="default" size="100%">eng</style></language><abstract><style face="normal" font="default" size="100%">Standard laptop computers are now capable of sizeable quantities of sound synthesis and sound processing, but low-latency, high quality, multichannel audio I/O has not been possible without a cumbersome external card cage.  CNMAT has developed a solution using the ubiquitous 100BaseT Ethernet that supports up to 10 channels of 24-bit audio, 64 channels of sample-synchronous control-rate gesture data, and 4 precisely time-stamped MIDI I/O streams. Latency measurements show that we can get signals into and back out of Max/MSP in under 7 milliseconds.   The central component in the device is a field programmable gate array (FPGA).   In addition to providing a variety of computer interface capabilities, the device can function as a cross-coder for a variety of protocols including GMICS.  This paper outlines the motivation, design, and implementation of the connectivity processor.</style></abstract></record></records></xml>